The present invention relates, in general, to methods of producing semiconductor devices, and more particularly, to methods of encapsulating semiconductor devices.
Chip-scale packaging (CSP) is a term used by the semiconductor industry for a semiconductor packaging technique. One example of chip-scale packaging is described in a article by Don Richmond, "Micro SMT Integrated Circuit Technical White Paper", Micro SMT Inc., Jan. 25, 1993. Chip-scale packages generally are formed by applying an encapsulant to an active surface of a semiconductor wafer, then thinning the back side of the semiconductor wafer followed by separating individual semiconductor die by sawing, scribing, or laser cutting through the back side of the wafer. Electrical contacts are also formed on the back side of the wafer so that the back side of the wafer can be used for attaching the semiconductor device to an interconnect mechanism such as a printed wiring board.
One problem with chip-scale packaging is warping or deformation of the semiconductor wafer during the manufacturing process. Generally, the encapsulant is applied to the active surface of the entire wafer and subsequently cured to form a protective layer on the active surface of the wafer. During this process, the encapsulant shrinks thereby warping the underlying semiconductor wafer. This warpage prevents accurate mask alignments during metallization, and other subsequent semiconductor processing techniques on the warped wafer.
Additionally, the thickness of the encapsulant varies across the surface of the wafer and typically has an edge-bead along the outside edges of the wafer. The thickness often varies greater than ten microns and results in poor alignments in subsequent processing operations. Also, the surface of the encapsulant typically is very rough and has peaks and valleys in various locations of the encapsulant surface. The difference between such peaks and valleys usually are greater than five microns. The non-uniform thickness and rough surface both prevent accurate mask alignments during subsequent semiconductor processing steps on the wafer.
Accordingly, it is desirable to have a semiconductor encapsulation method that does not warp the semiconductor wafer, that results in a substantially uniform thickness of the encapsulation layer on the semiconductor wafer, and that results in a substantially smooth surface.